CSE 2317 W5 Β· Class 1 Counters and registers
Sakeef Sani β†— ↓ PDF

CSE 2317Week 5Class 1Saturday Β· 11:00 AM – 12:20 PM80 min

Counters and registers

String flip-flops together and they count, divide, shift and remember words. Ripple or synchronous: the difference is when the outputs can be trusted. Class Test 1 in the last 20 minutes.

S present Β· L lecturer notes Β· β†’ next step Β· F full screen Β· P presenter window
01 Cold open 0–3 min

Seven, then… six, four, zero, eight

Last class's homework: two T flip-flops, each clocked by the one before, count. Add two more and you have a 4-bit counter.

It sits at 0111 = 7. The clock edge arrives. What values appear on the four outputs, in order, before it reaches 8?

Think deeper

Each flip-flop takes tpd = 20 ns to respond, and each is clocked by the previous output. List the outputs at 0, 20, 40, 60 and 80 ns.

Argue it in pairs for two minutes. There may be more than one defensible answer.

02 Concept 3–7 min

The ripple counter: each flip-flop clocks the next

  • n T flip-flops with T = 1 (or JK with J = K = 1). The clock drives only FF0; every Qi is the clock of FFi+1.
  • Negative-edge flip-flops: FFi+1 toggles when Qi falls 1 β†’ 0, exactly when binary counting carries: an up-counter. Clock the next stage from QΜ„i (or use positive-edge flip-flops) and it counts down.
  • Every stage halves the frequency: a free frequency divider.
N=2nΒ states,fQnβˆ’1=fclk2n,tsettle=n tpdN = 2^n\ \text{states},\qquad f_{Q_{n-1}} = \frac{f_{clk}}{2^n},\qquad t_{settle} = n\,t_{pd}
CLKQ0Q1Q2

Ideal (zero-delay) waveforms: Q2Q1Q0 counts 0, 1, 2 … 7. The real ones are shifted by one tpd more at each stage.

03 Live lab 7–12 min

Live lab: watch the carry ripple

Counters: ripple vs synchronous Negative-edge T flip-flops, one flip-flop delay = one small step. Watch the outputs just after each falling clock edge: a ripple counter passes through values that are not the count.
FF0T = 1Q0FF1T = 1Q0FF2T = 1Q0FF3T = 1Q1CLK
10008Q₃Qβ‚‚Q₁Qβ‚€
7β†’6β†’4β†’0β†’8
Settles afterup to 4 tpd
False states seen4
CLKQ0Q1Q2Q3
04 Worked example 12–17 min

Worked example: ripple delay and fmax

Given

A 4-bit ripple up-counter of negative-edge T flip-flops, tpd = 20 ns each. It holds 0111. The count is read by a circuit that needs it stable for a strobe time ts = 30 ns before the next edge.

Find

(a) The output values and when they occur after the clock edge. (b) The maximum clock frequency.

123456789edgeCLKQ0?Q1?Q2?Q3?

One slot = 20 ns. The clock falls at the marker.

Method: ripple counter delay (Mano; Taub & Schilling)

Solution

Predict the answer first. Then reveal one step at a time.

05 Concept 17–20 min

Mod-N: cut the count short

  • Choose the fewest flip-flops with 2n β‰₯ N. Detect the state N with a NAND of the Q's that are 1 in N, and feed it to every flip-flop's asynchronous CLRΜ„.
  • Decade (mod-10): N = 10 = 1010, so NAND(Q3, Q1). The counter reaches 1010, is cleared to 0000 within a few nanoseconds, and counts 0 … 9.
  • Price: state 1010 still appears, briefly, as a glitch. The 74LS90 decade counter is built this way.
00000100012001030011401005010160110701118100091001 101010CLRΜ„ β†’ 0000
From our lab

In the counter lab (slide 3), pick Mod-10 and watch 9 β†’ 8 β†’ 10 β†’ 0: the 10 lasts one gate delay.

06 Your turn 20–24 min

Your turn Β· 1: a mod-6 ripple counter

04:00
1 Exam CQ

Design a mod-6 ripple up-counter from negative-edge T flip-flops with active-low CLRΜ„.

(a) How many flip-flops? (b) Which gate drives CLRΜ„? (c) The clock is 60 kHz: what are the frequency and duty cycle of the top output?

Work it out first.
Press Solve when the class has an answer.

07 Concept 24–28 min

Synchronous counters: one clock for everyone

  • All flip-flops share the clock, so all change together, one tpcq after the edge. No ripple, no false states.
  • Binary up-counter: a bit toggles when every bit below it is 1:
T0=1,T1=Q0,T2=Q0Q1,T3=Q0Q1Q2Tclkβ‰₯tpcq+tAND+tsuT_0 = 1,\quad T_1 = Q_0,\quad T_2 = Q_0Q_1,\quad T_3 = Q_0Q_1Q_2 \qquad T_{clk} \ge t_{pcq} + t_{AND} + t_{su}

The minimum period no longer grows with n (with parallel AND gates). Any sequence at all can be designed with the excitation table:

Q β†’ Q⁺J KDT
0 β†’ 00 x00
0 β†’ 11 x11
1 β†’ 0x 101
1 β†’ 1x 010
Pro tip

Excitation = the characteristic table read backwards: "I need this transition; what inputs give it?" JK has the most x's, so the simplest gates.

08 Worked example 28–35 min

Worked example: a synchronous mod-5 counter from JK flip-flops

Given

JK flip-flops, common clock. Count 0, 1, 2, 3, 4, 0, …

Find

J and K for each flip-flop, and what happens if it powers up in an unused state.

Qβ‚‚Q₁Qβ‚€Q⁺Jβ‚‚Kβ‚‚J₁K₁Jβ‚€Kβ‚€
0000010x0x1x
0010100x1xx1
0100110xx01x
0111001xx1x1
100000x10x0x
101–111xxxxxxx

Method: counter design with the JK excitation table (Mano)

Solution

Predict the answer first. Then reveal one step at a time.

09 Live lab 35–38 min

Live lab: the same count, synchronously

Counters: ripple vs synchronous Negative-edge T flip-flops, one flip-flop delay = one small step. Watch the outputs just after each falling clock edge: a ripple counter passes through values that are not the count.
FF0T = 1Q0FF1T = Qβ‚€Q0FF2T = Qβ‚€Q₁Q0FF3T = Qβ‚€Q₁Qβ‚‚Q1CLK
10008Q₃Qβ‚‚Q₁Qβ‚€
7β†’8
Settles after1 tpd
False states seen1
CLKQ0Q1Q2Q3
10 Concept 38–42 min

Registers: words that move

  • A register is n D flip-flops on one clock: it stores an n-bit word. Connect each Q to the next D and it shifts one place per edge.
  • Four ways in and out: SISO (delay line), SIPO (serial β†’ parallel: receive a UART byte), PISO (parallel β†’ serial: send it), PIPO (plain storage).
  • Close the loop and it counts: ring counter (Qnβˆ’1 β†’ D0, one circulating 1, n states) and Johnson counter (QΜ„nβˆ’1 β†’ D0, 2n states).
Counter (n flip-flops)StatesDecode
Binary2nn-input AND
Ringnnone (one-hot)
Johnson2n2-input AND
Gotcha

Ring and Johnson counters have unused states too (16 βˆ’ 4 = 12 for a 4-bit ring). Power up in one and it never recovers unless you design it to.

11 Live lab 42–46 min

Live lab: shift, ring, twist

Shift registers, ring and Johnson counters At every rising edge each flip-flop copies its left neighbour. Feed the last output back to the first and the register counts. Click a flip-flop to corrupt its bit.
in0DQ0Q0DQ0Q1DQ0Q2DQ1Q3CLK
Qβ‚€Q₁Qβ‚‚Q₃0001

Recent states, newest first:

00010011011011001000000100110110
CLKDβ‚€Q0Q1Q2Q3
12 Your turn 46–50 min

Your turn Β· 2: the Johnson counter

04:00
2 Exam CQ

A 4-bit shift register, Q̄₃ fed back to Dβ‚€, starts at 0000 and is clocked at 8 MHz.

(a) List the states until it repeats. (b) Frequency and duty of each output? (c) Show that each state can be decoded with a 2-input gate.

Work it out first.
Press Solve when the class has an answer.

13 Real world 50–53 min

Real world: clocks, signs and the prayer-time display

The digital clock above the mosque door or on the wall of a Dhaka pharmacy is counters all the way down: a 32.768 kHz crystal, a 15-stage ripple divider (215 = 32,768) giving exactly 1 Hz, then mod-10 and mod-6 counters for seconds and minutes, mod-12 or mod-24 for hours.

The scrolling LED sign over a shop is shift registers: a microcontroller pushes each column serially into a chain of 74HC595s, then latches all outputs at once.

BME corner

A pulse oximeter or ECG monitor computes heart rate by counting clock ticks between beats: a synchronous counter, read on a known edge. A ripple counter read mid-change could report 0 ms or 1000 ms for one beat.

14 Pop quiz 53–57 min

Pop quiz

Score 0

Question 1 / 5

A 5-bit ripple counter is clocked at 1 MHz. The frequency at the last output (Q4) is…

15 Recap 57–60 min

Three things to remember

01

Ripple: each flip-flop clocks the next. Simple, divides by 2n, but settles nΒ·tpd after the edge and shows false states.

02

Synchronous: one clock, design with the excitation table (JK: 0x, 1x, x1, x0), check unused states. Mod-N ripple: NAND the 1-bits of N into CLRΜ„.

03

Registers store and shift words (SISO, SIPO, PISO, PIPO). Ring: n states, Johnson: 2n states, decoded by 2-input gates.

Pro tip

Homework: design a synchronous mod-6 counter (0 … 5) with D flip-flops and check its unused states. Next class: memories and PLAs.

16 Recap 60–80 min

Class Test 1

Class Test 1 Β· 20 minutes
20:00

Covers Weeks 1–4

Diode gates (DRL), RTL and DTL Β· the BJT switch and MOS gates Β· TTL, ECL, IΒ²L and CMOS Β· latches and flip-flops (timing diagrams, characteristic equations, setup and hold).

Rules

Closed book, answer on the question paper. Calculators allowed, phones away. Show the working for the calculation questions.

Questions are handed out on paper. Today's counters are not in this test.