One byte out of 137 billion
Your phone has 128 GB of storage: about 137 billion bytes.
To read one particular byte, the processor has to name it. How many wires (address bits) does it need? And what, physically, is a stored 1?
Today's four cells: the diode from Week 1, the latch from Week 4, a capacitor, and a MOSFET from Week 2 with a trapped charge.
Every memory: decoder, word lines, bit lines
- 2k words × n bits. k address bits go into a decoder that raises exactly one word line.
- The cells on that line put their bits on the n bit lines (read) or take them from there (write).
- Control: CS̄ (chip select), OE̅ (output enable, drives the data bus), WE̅ or R/W̄.
| Type | Cell | Volatile | Write |
|---|---|---|---|
| Mask ROM | diode / transistor present or not | no | at the factory |
| PROM | fuse | no | once |
| EPROM | floating gate | no | UV erase |
| EEPROM / Flash | floating gate | no | electrically |
| SRAM | 6-transistor latch | yes | any time, fast |
| DRAM | 1 transistor + 1 capacitor | yes | any time, refresh |
Worked example: building 256K × 16 from 64K × 8 chips
Given
64K × 8 memory chips with active-low CS̄. Any decoders.
Find
How many chips, how the address lines are connected, and which addresses row 2 answers.
Method: memory expansion: width and depth (Mano)
Solution
Predict the answer first. Then reveal one step at a time.
ROM: a grid of diodes
- Word lines run across, bit lines run down; each bit line has a pull-down resistor.
- The decoder drives the selected word line HIGH (all others LOW). Where a diode joins that word line to a bit line, it conducts: the bit line rises to ≈ VH − 0.7 V, a 1. No diode: the resistor holds it at 0.
- Each bit line is a diode OR (Week 1!) of the word lines that have a diode on it. A ROM is a decoder (all minterms) followed by OR gates.
Mask ROM: the factory leaves diodes (today: transistors) in or out. PROM: every crosspoint has a diode in series with a fuse; you blow the fuses of the 0s. EPROM / flash: the switch is a MOSFET whose threshold is set by charge on a floating gate.
Diodes are essential: a plain wire at a crosspoint would short the selected word line to every other word line through the bit lines.
Live lab: read and program a diode ROM
| A | D5…D0 | |
|---|---|---|
| 000 | 000000 | 0 |
| 001 | 000001 | 1 |
| 010 | 000100 | 4 |
| 011 | 001001 | 9 |
| 100 | 010000 | 16 |
| 101 | 011001 | 25 |
| 110 | 100100 | 36 |
| 111 | 110001 | 49 |
13 diodes = 13 stored 1s out of 48 bits.
Worked example: a full adder in an 8 × 2 ROM
Given
A ROM with 3 address inputs and 2 outputs (8 words × 2 bits), diode matrix.
Find
Its contents for a full adder (S, Cout) and the number of diodes.
Method: combinational logic with ROM (Mano)
Solution
Predict the answer first. Then reveal one step at a time.
RAM: a latch or a capacitor at every crosspoint
SRAM: 6 transistors
Two cross-coupled CMOS inverters (the bistable latch of Week 4) hold the bit; two nMOS access transistors connect it to BL and BL̄ when the word line is high. Holds as long as power is on, no refresh, fast (cache memory).
DRAM: 1 transistor + 1 capacitor
A charged capacitor (≈ 25 fF) is a 1. Reading connects it to the bit line, whose sense amplifier sees a tiny voltage change: the read is destructive, so the row is written back. Leakage drains it, so every row is refreshed every 64 ms. Tiny cell: main memory.
Live lab: refresh, or lose the bit
Overhead = 8192 rows × 50 ns ÷ 64 ms: the fraction of time the memory is busy refreshing instead of answering the processor.
Worked example: how often must DRAM refresh?
Given
Cell capacitance C = 25 fF, written to 1.2 V, sensed correctly while above 0.6 V. Worst-case leakage I = 0.1 pA. The chip has 8192 rows; refreshing one row takes 50 ns.
Find
The retention time, the margin over the 64 ms standard, and the refresh overhead.
Method: DRAM retention and refresh (Taub & Schilling)
Solution
Predict the answer first. Then reveal one step at a time.
Your turn · 1: 32K × 8 from 8K × 4
Build a 32K × 8 memory from 8K × 4 chips.
(a) How many chips? (b) How many address lines, and how are they connected? (c) Which row of chips answers address 5A3Ch?
Work it out first.
Press Solve when the class has an answer.
PLA: program the logic, not the data
- A ROM generates every minterm (2n of them) and ORs the ones you want. Most functions need only a few product terms.
- A PLA has a programmable AND array (make only the product terms you need, from inputs and their complements) and a programmable OR array (sum them into each output). Shared terms are made once.
- Size: n inputs, k product terms, m outputs:
| Device | AND array | OR array |
|---|---|---|
| PROM | fixed (full decoder) | programmable |
| PLA | programmable | programmable |
| PAL / GAL | programmable | fixed |
Write the functions as minimised sums of products first, and look for product terms the outputs can share.
Live lab: program a PLA
F₁ = AC + BC
F₂ = AC + AB̄
| ABC | F₁ | F₂ |
|---|---|---|
| 000 | 0 | 0 |
| 001 | 0 | 0 |
| 010 | 0 | 0 |
| 011 | 1 | 0 |
| 100 | 0 | 1 |
| 101 | 1 | 1 |
| 110 | 0 | 0 |
| 111 | 1 | 1 |
3 of 8 product terms used · 10 connections.
Worked example: a PLA programming table
Given
F₁(A, B, C) = Σm(3, 5, 7) and F₂(A, B, C) = Σm(4, 5, 7).
Find
The minimised functions and the PLA programming table with the fewest product terms.
Method: PLA programming table (Mano)
Solution
Predict the answer first. Then reveal one step at a time.
Your turn · 2: PLA or ROM?
The classic 82S100 PLA has 16 inputs, 48 product terms and 8 outputs.
(a) How many programmable crosspoints does it have? (b) How many bits would a ROM need to implement any 8 functions of the same 16 inputs? (c) When would you choose each?
Work it out first.
Press Solve when the class has an answer.
Critical thinking · the seven-segment decoder
A BCD to 7-segment decoder: 4 inputs, 7 outputs. ROM or PLA?
Argue it in pairs for two minutes. There may be more than one defensible answer.
Why did FPGAs replace PLAs and PALs for big designs?
Argue it in pairs for two minutes. There may be more than one defensible answer.
Real world: memories you carry
- Phone: SRAM caches inside the processor, a few GB of DRAM refreshed every 64 ms (32 ms when hot), and 128 GB of 3D NAND flash, each cell holding 3–4 bits as different amounts of trapped charge.
- Cards: bank cards, SIM cards and smart ID cards keep keys and records in EEPROM on the chip: non-volatile, rewritable byte by byte, no battery.
- Every microcontroller: flash for the program, SRAM for variables, a little EEPROM for settings.
A pacemaker stores its pacing settings and an event log in EEPROM and its firmware in flash: they must survive a battery change and years of use. Flash endurance (≈ 10⁴–10⁵ erase cycles) is a design limit for medical loggers.
Pop quiz
Question 1 / 5
A memory chip has 12 address lines and 8 data lines. Its capacity is…
Three things to remember
Memory = decoder + word lines + bit lines. 2k × n. Width: chips side by side; depth: decode the top address bits into CS̄.
Cells: diode/fuse (ROM, PROM), floating gate (EPROM, flash), 6T latch (SRAM), 1T1C (DRAM, refresh every 64 ms).
PLA: programmable AND + OR, share product terms; PAL fixes the OR, PROM fixes the AND. ROM for tables, PLA for many inputs and few terms.
Implement F₁ = Σm(0, 1, 2, 3, 7) and F₂ = Σm(0, 1, 2, 3, 4) in a PLA with the fewest product terms. Give the programming table, and verify it in the PLA lab.
Work it out first.
Press Solve when the class has an answer.